RISC-V Architecture Overview

1. Core ideas

RV32I is the 32-bit base integer ISA. It uses 32 general-purpose registers (x0..x31) and a load/store model. Only loads and stores touch memory; arithmetic stays in registers.

2. Registers at a glance

 1
 2
 3
 4
 5
 6
 7
 8
 9
10

x0  = zero (always 0)
x1  = ra   (return address)
x2  = sp   (stack pointer)
x3  = gp   (global pointer)
x4  = tp   (thread pointer)
x5..x7    = temporaries (t0..t2)
x8..x9    = saved (s0/fp, s1)
x10..x17  = args/return (a0..a7)
x18..x27  = saved (s2..s11)
x28..x31  = temporaries (t3..t6)

3. Instruction formats

flowchart LR
  I["Immediate"] -->|addi/lw/jalr| I1["imm[11:0] rs1 funct3 rd opcode"]
  R["Register"] -->|add/sub| R1["funct7 rs2 rs1 funct3 rd opcode"]
  S["Store"] -->|sw/sb| S1["imm[11:5] rs2 rs1 funct3 imm[4:0] opcode"]
  B["Branch"] -->|beq/bne| B1["imm rs2 rs1 funct3 imm opcode"]

4. Additional resources

• For more details, see the RISC-V spec.
• Another useful and concise resource is RISC-V Card.

5. Memory map in QEMU virt

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2

0x8000_0000  RAM (we place code + data here)
0x1000_0000  UART0 (MMIO)

6. Exercises

1. Identify which registers are caller-saved vs callee-saved.
2. Look up one instruction format in the RISC-V Card spec and map each field by name.

7. Summary

• RV32I provides a small, clean base ISA.
• The register file is fixed and conventions give registers roles.
• QEMU virt exposes a simple RAM + UART memory map.