Preface

1. Purpose and scope

This book is a hands-on, bare-metal introduction to RISC-V assembly programming. You will build and run small RV32 programs under QEMU system-mode using the riscv64-unknown-elf-gcc cross-toolchain. There is no real hardware assumed, and there is no libc available, so every example stays freestanding and prints through the QEMU virt UART.

2. Who this is for

• Readers with basic programming experience who want to understand assembly and bare-metal workflows.
• Engineers who want a repeatable, emulator-first workflow for learning and debugging RISC-V.

3. How to use this book

• Every code block that names a file lives in GitHub RISC-V Experiments Repository.
• Each chapter ends with exercises and a short summary.
• All build commands use riscv64-unknown-elf-gcc and run under qemu-system-riscv32, check the chapter Setting Up the Toolchain for details.

4. Contact

Feedback and questions are welcome. Make a comment, open an issue or a pull request on the repository and include the chapter name and section so it is easy to reproduce.

5. Exercises

1. Clone the repository for this book from GitHub RISC-V Experiments Repository.
2. Locate the src/ directory and skim the file list.

6. Summary

• This book is bare-metal, RV32, and QEMU-only.
• You will use riscv64-unknown-elf-gcc for every build.
• Exercises and summaries are included in each chapter.